Complementary metal oxide semiconductor (CMOS) field effect transistor (FET) technology involves the formation and utilization of n-channel FETs (NMOS) and p-channel FETs (PMOS) in combination (MOSFETs) to form low current, high performance integrated circuits.
In sub-micron semiconductor technology, the use of self-aligned silicide processes has become widely accepted to minimize device series resistance. The silicide process is defined by introducing metal into silicon, which may overcome the high resistivity between metal and polysilicon gates and source/drain regions in MOSFETs. In the self-aligned silicide process, the polysilicon is deposited and patterned followed by a metal deposition. Then, the silicide is formed by thermal reaction. A disadvantage of the silicide process is the exacerbation of the stress related defects formed in the source/drain region.
A pre-amorphous implant (PAI) may confine the silicide formation to the PAI-induced amorphous layer. While the use of a PAI process for relieving stress-retarded reaction and increasing nucleation density is known, there are disadvantages with the PAI process. One such disadvantage of the PAI process is that the PAI process may degrade source/drain conductivity. Typical anneal processes do not cure this deficiency. Yet another disadvantage may be the degraded resistance in PMOS gated diodes, causing a degraded PMOS performance.